(1) Field of the Invention
The present invention relates to a static type semiconductor memory device and more particularly to a semiconductor memory device which is used, for example, in an electronic computer and which is operated in a power down mode when the chip of the semiconductor memory device is not selected.
(2) Description of the Prior Art
The static type semiconductor RAM device of recent years has mostly been a gated static type RAM device having a power down mode. In order to decrease power consumption, such a gated static type RAM device is operated in the power down mode when the memory chip of the gated static RAM device is not selected, i.e., when the memory chip is on standby. When the memory chip is selected, the RAM device is operated in a usual operating mode in which power consumption is larger than that in the power down mode. The memory chip is selected when a chip select signal CS applied thereto is low and is not selected when the chip select signal CS is high. In the RAM device, power is saved, for example, by turning off the power source supplied to peripheral circuits thereof, such as decoder circuits, by using output signals from buffer amplifiers which receive the chip select signal CS. In this case, only the power source supplied to memory cells is kept in a turned on condition. When the power source to the decoder circuits is turned off, all the memory cells are disconnected from bit line pairs and all the bit line pairs are disconnected from a data bus pair. The bit line pairs and the data bus pair are then pulled up to a high potential level by respective pull up circuits. However, the size of the transistors used in the pull up circuits has become smaller due to the recent increase in the degree of integration of the RAM device, and the gm of each of the transistors of the pull up circuits has become small, so that the pull up speeds of the bit line pairs and the data bus pair have been reduced. The potential of a bit line of a selected bit line pair is low and the potential of the other bit line of the selected bit line pair is high, so that the potential of a data bus of the data bus pair which receives the potentials of the selected bit line pair is low and the potential of the other data bus of the data bus pair is high. Therefore, it is difficult to rapidly pull up the potentials of the bit line pair and data bus pair to the same high potential level after the power source of the decoder circuits is turned off in the power down mode, and the potentials of the bit lines of the selected pair or the potentials of the data buses are different from each other at the beginning of the power down mode.
Therefore, in a conventional static type semiconductor RAM device, when the memory chip thereof is reactivated a short time after the memory chip is at standby, i.e., in the power down mode, the readout speed of the RAM device becomes low because of the above-mentioned difference in potential of the data bus lines. When the condition of the memory chip has changed from a non-selected condition to a selected condition and readout is effected, the readout speed is also decreased as a result of the delay in activation of the peripheral circuits after the operating voltage is supplied thereto due to the change of the chip select signal CS from high to low. Therefore, the access time of the conventional RAM device, when the condition of the memory chip has changed from the non-selected condition to the selected condition, is too long.